In the context of this specification, the term “sub-rate” means either a sub-set of bits in a time slot, or alternatively, refers to the associated data rate which corresponds to the aforementioned sub-set of bits being transmitted on a data bus. The particular meaning to be adopted will be clear from the context in which the term is used.
Typical digital cross-connection equipment provides for cross-connection from high speed input data buses to high speed output data buses and/or to lower speed output data buses. The high speed data buses are typically multi-master buses or point-to-point buses. The cross-connection operation can be performed either directly, or typically via buffering RAM. Cross-connection is generally performed at the system bus width or granularity. Thus, an incoming data bus having a data rate of M bits per second typically has a bus “width” N bits wide. The cross-connection function can cross-connect the input bus running at M bits per second to an output bus running at m bits per second (where m is less than M). The output bus and the input bus are typically both N bits wide. The width of the output data bus can however be smaller (eg. n bits wide, where n is less than N), this finer granularity requiring more control lines to the cross-connect. Free cross-connectability can be achieved from any incoming bit on the incoming bus to any outgoing bit on the outgoing bus, but this results in poor efficiency in control memory, particularly if most cross-connections are to be performed at the aforementioned system granularity, ie. N bits wide.
Two typical cross-connect architectures have been adopted. In the first architecture, all data in the high capacity input bus is stored in a buffering RAM, from which it is thereafter cross-connected into output buses. Alternatively, data may be directly cross-connected from the input bus, and thereafter written into buffer RAM. Both of these architectures have disadvantages.
When the entire content of the high speed input bus is buffered before cross-=connection, storage capacity is inefficiently utilised, since all data is stored, but not all data will be used, ie. cross-connected. This approach results in wasted silicon area if cross-connection apparatus is implemented in monolithic integrated circuits. This inefficiency is particularly noticeable as the difference in speed, ie. the bit-rate between input and output buses increases.
The second architecture, which performs cross-connection directly from the input bus, makes use of less buffering memory, providing a solution to the memory inefficiency previously described. This second architecture, however, requires several cross-connections for connecting the entire N bit word, and thus the cross-connection state-machine typically runs at a clock rate which can be up to N times faster than the input bus.